wb_i2c_slave - An I2C to Wishbone Bridge for FPGAs
This is the project homepage for wb_i2c_slave, an I2C slave device implementation that acts as a master for the Wishbone bus. The engine was designed for FPGAs and written in VHDL.
Last updated: $Date: 2013/01/05 22:27:54 $.
The wb_i2c_slave is an I2C slave implementation for FPGAs that translates I2C requests to the Wishbone bus. It allows clients to generate cycles on the Wishbone bus in an FPGA design through the I2C protocol. The design is supposed to be configurable through generics, but there hasn't been a lot of test coverage for values other than the defaults.
The module's internal architecture is divided into an I2C bus sampling logic and a Wishbone master interface logic.
The module doesn't impose a maximum speed requirement on the I2C clock. Because the module samples the I2C clock based on its own logic clock, the maximum I2C speed is determined by the ratio between I2C clock and logic clock. Internally, the I2C clock is not only sampled but also debounced. Sampling occurs at the speed of the logic clock; debouncing works through an eight-bit shift register. In effect, the logic clock should run faster than the I2C clock by at least a factor of 16. Higher factors will work better.
Using the wb_i2c_slave component in your VHDL design is as easy as declaring and instantiating any other component. Below is the VHDL entity declaration of the component.
The design is customizable through a few generics, which are described in the following table.
|dat_sz||Width of Wishbone data bus. This also determines the size of the internal I2C registers. The module will probably not work if this generic is set to a value other than 8.|
|off_sz||Determines the width Wishbone address bus. This also affects the width of the I2C address register.|
|pg_sz||Determines the page size of the Wishbone bus, therefore the granulatiry of addressing. Given in powers of two, i.e. one page contains 2**pg_sz nibbles (size of nibble == dat_sz). The module will probably not work correctly if this is set to something other than 1.|
|increment_target||Increment Target Register. If set, consecutive read or write access cycles will increment the internal target register by one.|
|i2c_adr||I2C bus address of the device.|
The module does not have user accessible registers.
An example I2C write cycle sequence understood by this module looks like this:
If the increment_target generic is set to 1, this will generate a write cycle writing [Data Byte #0] to Wishbone address [MSB..LSB] followed by a write cycle writing [Data Byte #1] to the Wishbone address ([MSB..LSB] + 1), etc.
If the increment_target generic is set to 0, this will generate a write cycle writing [Data Byte #0] to Wishbone address [MSB..LSB] followed by a write cycle writing [Data Byte #1] to the same Wishbone address.
An example I2C read cycle sequence understood by this module looks like this:
If the increment_target generic is set to 1, this will generate a read cycle reading from Wishbone address [MSB..LSB] returning [Data Byte #0] followed by a read cycle from the Wishbone address ([MSB..LSB] + 1) returning [Data Byte #1], etc.
If the increment_target generic is set to 0, this will generate read cycles repeatedly reading from Wishbone address [MSB..LSB] returning [Data Byte #0] followed by returning [Data Byte #1], etc.
The device will stall the I2C clock while Wishbone transfers are in progress.
The module acts as a Wishbone master. It generates classic read/write cycles and does not support classic pipelined read/write operations. Thus, it does not honor the stall signal which may be generated by slaves.
The Wishbone cyc signal is asserted as soon as the I2C logic has decoded the I2C address and determined that the module is being targeted. It is released once the I2C transfer is complete and the logic has entered the idle state again. This behavior is useful if the Wishbone interface is connected to an actual bus with multiple master/slave participants which requires an arbiter. Keeping the cyc signal asserted ensures that the Wishbone bus is held exclusively while the I2C transfer is in progress, i.e. no other Wishbone master can issue transfers in parallel.
The Wishbone stb signal is asserted only while a Wishbone transfer is in progress. The signal is being kept active until the Wishbone master logic has seen a response from a slave, i.e. either an ack or an error response.
The module does not contain any kind of watchdog logic. Hence, the described I2C and Wishbone behavior can effectively lock up all Wishbone logic if a Wishbone slave fails to generate a response to a generated Wishbone cycle. This is the case if an I2C transfer attempts to target a Wishbone address to which no slave is registered.
Because the device stalls the I2C clock while Wishbone transfers are in progress, such a situation can also block the I2C bus.
Resolving this situation is outside the scope of the wb_i2c_slave logic. If the behavior is dangerous or undesirable in your logic design, I suggest you resolve it in the Wishbone interconnect logic, e.g. by building watchdog logic into your Wishbone interconnect.
Below are the links to the VHDL files.
- I2C Interface, i2c_sync.vhd
- Wishbone Master Interface, wb_i2c_slave.vhd
- Address Register, register_addr.vhd
- Shift Left Register, register_shl.vhd
- Shift Right Register with parallel Load, register_shr_pload.vhd
Here are a few links related to this project.
- Wikipedia Article on the Wishbone Bus.
- The Wishbone Bus Specification, Rev. B4
- Wikipedia Article on the I2C Bus.
- The I2C Bus Specification, Vers. 2.1 (January 2000).
Contact the author Philip Schulz by Email.